Semiconductor package and method of manufacturing the same

ABSTRACT

A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

PRIORITY CLAIM

This application is a continuation-in-part of, and claims the benefit of, U.S. patent application Ser. No. 13/585,500, filed on Aug. 14, 2012, titled “SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME” which is hereby incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to semiconductor packages and, more particularly, to methods of manufacturing semiconductor packages.

BACKGROUND

Modern integrated circuits are made of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Flip-chip packaging utilizes bumps to establish electrical contact between a chip's input/output (I/O) pads and the substrate or lead frame of the package. Structurally, a bump structure usually refers to a bump and an “under bump metallurgy” (UBM) located between the bump and an I/O pad. Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes, and ball placement or ball drop process is utilized in the WLCSP technology.

DESCRIPTION OF THE DRAWINGS

FIGS. 1A-6 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment;

FIG. 6A is a cross-sectional diagram illustrating an individual chip with a pillar bump formed by using the method as shown in FIGS. 1A-6 according to an embodiment;

FIG. 6B is a top view of the metal pillar shown in FIG. 6A according to an embodiment;

FIG. 6C is a top view of the metal pillar shown in FIG. 6A according to an embodiment;

FIGS. 7-12 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment;

FIG. 12A is a cross-sectional diagram illustrating an individual chip with a pillar bump formed by using the method as shown in FIGS. 7-12 according to an embodiment;

FIGS. 13-15 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment; and

FIG. 15A is a cross-sectional diagram illustrating an individual chip with a pillar bump formed by using the method as shown in FIGS. 13-15 according to an embodiment.

DETAILED DESCRIPTION

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the disclosure. Embodiments described herein relate to bumps for use with semiconductor devices. As will be discussed below, embodiments are disclosed that utilize a bump for the purpose of attaching one substrate to another substrate, wherein each substrate may be a die, wafer, interposer substrate, printed circuit board, packaging substrate, or the like, thereby allowing for die-to-die, wafer-to-die, wafer-to-wafer, die or wafer to interposer substrate or printed circuit board or packaging substrate, or the like. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements.

Reference will now be made in detail to exemplary embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, an apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Further, when a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.

FIGS. 1A-6 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment.

With reference to FIG. 1A and FIG. 1B, a semiconductor wafer 100 including a plurality of chips (or dies) 10A and 10B with electrical circuitry and bumps manufactured thereon is provided. FIG. 1A is a top view of the semiconductor wafer 100 with chips 10A and 10 B according to an embodiment, and FIG. 1B is a cross-sectional view taken along the line A-A shown in FIG. 1A. The semiconductor wafer 100 comprises an array of chips separated from each other by two sets of intersecting scribe line regions 12. One set of scribe line regions 12 extend along a first direction and a second set of scribe line regions 12 extend along a second direction. In accordance with an embodiment, the chips 10A and 10B have a substantially identical structure. The cross-section view illustrates a first chip 10A formed on a first chip region I and a second chip 10B formed a second chip region II, and the chip regions I and II are separated by the scribe line region 12. The structures of the chips 10A and 10B formed on the chips regions I and II are described in detail below.

In manufacturing the chips 10A and 10B, semiconductor processes are performed on a semiconductor substrate 14 to form an electrical circuitry, a dielectric layer 16, contact pads 18, a first passivation layer 20, a second passivation layer 22, under-bump metallization (UBM) layers 24 and bumps 26. In an at least one embodiment, the layers 16, 20, and 22 are also formed to extend onto the scribe line region 12. The semiconductor substrate 14 may include, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. The electrical circuitry (not shown) formed in the semiconductor substrate 14 may be any type of circuitry suitable for a particular application. In some embodiments, the electrical circuitry includes electrical devices having one or more dielectric layers overlying the electrical devices. Metal layers may be formed between dielectric layers to route electrical signals between the electrical devices. Electrical devices may also be formed in one or more dielectric layers. For example, the electrical circuitry may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like, interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of some illustrative embodiments and are not meant to limit the disclosure in any manner. Other circuitry may be used as appropriate for a given application.

The dielectric layer 16 may be formed, for example, of a low dielectric constant (low-K) dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiO_(x)C_(y), Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method, such as spinning, chemical vapor deposition (CVD), and/or plasma-enhanced CVD (PECVD). In some embodiments, the dielectric layer 16 may comprise a plurality of layers of dielectric materials. Metal lines and/or vias (not shown) may be formed inside the dielectric layer 16 to provide an electrical connection to the electrical circuitry formed in the semiconductor substrate 14. In some embodiments, the uppermost dielectric layer is formed of a dielectric material, such as silicon nitride, silicon oxide, undoped silicon glass, and the like.

The contact pads 18 are formed on the dielectric layer 16 to electrically connect the metal lines or vias inside the dielectric layer 16. In some embodiments, the contact pads 18 may be formed of aluminum, aluminum copper, aluminum alloys, copper, copper alloys, or the like. One or more passivation layers, such as the first passivation layer 20 and the second passivation layer 22, are formed over the dielectric layer 16 and patterned to expose portions of the contact pads 18 respectively. In some embodiments, the first passivation layer 20 is formed of a dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride or a non-porous material by any suitable method, such as CVD, PVD, or the like. In an embodiment, the first passivation layer 20 is formed to cover a peripheral portion of each contact pad 18, and to expose a central portion of each contact pad 18 through openings in the first passivation layer 20. The first passivation layer 20 may be a single layer or a laminated layer. The second passivation layer 22 is formed over the first passivation layer 20 and patterned to expose portions of the contact pads 18 respectively. In some embodiments, the second passivation layer 22 may be, for example, a polymer layer, which is patterned to form openings, through which the contact pads 18 are exposed. In some embodiments, the polymer layer is formed of a polymer material such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like, although other relatively soft, often organic, dielectric materials can also be used. The formation methods include spin coating or other methods.

The UBM layers 24 are formed on the exposed portions of the corresponding contact pads 18. In some embodiments, the UBM layer 24 extends to a surface of the second passivation layer 22 adjacent to the contact pad 18. The formation methods of the UBM layer 24 include photoresist coating, lithography, wet or dry etching, and/or the like. In an embodiment, the UBM layer 24 includes at least one metallization layer comprising titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), copper alloys, nickel (Ni), tin (Sn), gold (Au), or combinations thereof. In some embodiments, the UBM layer 24 includes at least one Ti-containing layer and at least one Cu-containing layer.

The bumps 26 are formed on the corresponding UBM layers 24. The bump 26 can be a spherical bump or a pillar bump formed of a conductive material including at least one of solder, Cu, Ni or Au. In an embodiment, the bump 26 is a solder bump formed by attaching a solder ball to the UBM layer 24 and then thermally reflowing the solder material. In an embodiment, the solder bump is formed by plating a solder layer using photolithography technologies followed by reflow processes. In an embodiment, the solder bump has a diameter greater than about 200 μm. In some embodiments, the solder bump includes a lead-free pre-solder layer, SnAg, or a solder material including alloys of tin, lead, silver, copper, nickel, bismuth, or combinations thereof.

With reference to FIG. 2A and FIG. 2B, a grooving process is performed on the wafer 100 to form grooves 28 on the scribe line regions 12. FIG. 2A is a top view of the semiconductor wafer 100 with the grooves 28 according to an embodiment, and FIG. 2B is a cross-sectional view taken along the line B-B shown in FIG. 2A. The grooving process removes portions of the second passivation layer 22, the first passivation layer 20, the dielectric layer 16 and the semiconductor substrate 14 within the scribe line regions 12. In an embodiment, the grooves 28 are formed by irradiating the scribe line regions 12 are with a laser beam. The grooves 28 on the wafer 100 can be formed in a continuous manner on the scribe line regions 12 according to one embodiment, such that the planar layout of the groove 28 is substantially similar to that of the intersecting scribe line regions 12. For example, first sets of grooves 28 extend along the first direction and second sets of grooves extend along the second direction. In some embodiments, the grooves 28 on the wafer 100 can be formed in a discontinuous manner in the scribe line regions 12 and separated from each other by a distance. As a result, at least one groove 28 is formed on the scribe line region 12 between two adjacent chip regions I and II. In an embodiment, the groove 28 of a width W1 penetrates the layers 22, 20 and 16 and reaches to a depth D1 of the semiconductor substrate 14. The depth D1 is less than a thickness T1 of the semiconductor substrate 14, and the width W1 is less than a width W2 of the scribe line region 12. In an embodiment, the depth D1 is equal to or greater than about 10 μm.

Next, as shown in FIG. 3, a molding compound layer 30 is applied on the structure depicted in FIG. 2B to cover the second passivation layer 22 and fill the grooves 28, where each bump 26 is partially buried in the molding compound layer 30. In an embodiment, the bump 26 including the lower portion 26L and the upper portion 26U, and the molding compound layer 30 is in physical contact with a lower portion 26L of the bump 26, while the upper portion 26U of the bump 26 is exposed and protrudes from a top surface 30A of the molding compound layer 30. In some embodiments, the molding compound layer 30 may be in physical contact with the second passivation layer 22 and/or the UBM layers 24. In some embodiments, the thickness (T2) of the molding compound layer 30 is between about ¼ to ¾ of the height (H) of the bump 26. In an embodiment, the molding compound layer 30 is formed by applying a liquid molding compound and performing a curing process to cure and solidify the liquid molding compound. In some embodiments, a release film or a soft material may be applied on the liquid molding compound. Pressure is applied on the release film on the liquid molding compound, so that a portion of the bump 26 is pressed into the release film. Furthermore, the pressure applied on the release film may push some of liquid molding compound downward. While the pressure is applied to the release film pushing against the bump and the liquid molding compound, a curing may be performed to cure and solidify liquid molding compound. Thereafter, the release film is peeled off the molding compound layer 30.

Then, as shown in FIG. 4, the wafer 100 is positioned upside down and attached to a tape 32, followed by performing a grinding process 34 on the backside of the semiconductor substrate 14, so as to thin down the thickness of the semiconductor substrate 14. In an embodiment, the thinned substrate 14″ has a thickness T3 which is less than the thickness T1, but greater than the depth D1 of the groove 28.

After detaching the tape 32 as depicted in FIG. 5, a singulation process is performed on the scribe line regions 12 to separate the individual chips 10 from the wafer 100. As depicted in FIG. 5, the dotted line 36 indicates the singulation process performed on the scribe line region 12, which passes through the molding compound layer 30 within the groove 28 and passes through the semiconductor substrate 14 underlying the groove 28. After the singulation process, an example individual chip 10 is shown as FIG. 6. The molding compound layer 30 covers the lower portion 26L of the bump 26, the surface of the second passivation layer 22, and the sidewalls S22, S20 and S 16 of the layers 22, 20 and 16. In addition, in the individual chip 10, the thinned substrate 14″ includes an upper sidewall S1 adjacent to the sidewall S16 of the dielectric layer 16, a lower sidewall S2 adjacent to the backside 14B of the thinned substrate 14″, and a surface region S3 extending from the upper sidewall S1 to the lower sidewall S2. The upper sidewall S1 and the surface region S3 are parts of the groove 28 created by the grooving process, resulting in a recess region 14R at the edge of the thinned substrate 14″. The lower sidewall S2 is formed by the singulation process.

In an embodiment, the upper sidewall Si is substantially leveled with at least one of the sidewalls S16, S20 and S22 of the layers 16, 20 and 22, and the lower sidewall S2 is substantially leveled with the sidewall S30 of the molding compound layer 30. In an embodiment, the upper sidewall S1 has the depth substantially the same as the depth D1. In an embodiment, the molding compound layer 30 covers the upper sidewall S1 and the surface region S3 of the thinned substrate 14″. In an embodiment, the molding compound layer 30 fills the recess region 14R of the thinned substrate 14″. The individual chips 10 may be used in many different situations. For example, the individual chip 10 may be used in a die-to-die bonding configuration, a die-to-wafer bonding configuration, die-level packaging, or the like. In some embodiments, the individual chip 10 is flipped upside down and attached to another substrate, for example, a chip, an interposer, a printed circuit board (PCB), or any other package substrates.

According to the embodiments depicted in FIG. 6, the molding compound layer 30 fully covers the upper sidewall S1 and surface region S3 of the semiconductor substrate 14 adjacent to the chip edge to provide the bump 26 with a strong adhesive strength so as to eliminate the chip crack issue during the singulation process. Also the molding compound layer 30 covers the lower portion 26L of the bump 26, which can provide a strong package structure for attaching to another substrate. Moreover, using laser grooving process prior to the chip singulation process can eliminate or reduce the initial crack points in the dielectric layer 16, the passivation layers 20 and 22 and the edge of the chip 10 so that the device reliability is improved.

For achieving fine pitch requirements, the bump 26 can be formed as a pillar bump according to some embodiments. FIG. 6A is a cross-sectional diagram illustrating the individual chip 10 with a pillar bump 26A. In an embodiment, the pillar bump 26A includes a metal pillar 26I formed on the UBM layer 24 and a cap layer 26II formed on the metal pillar 26I. The molding compound 30 covers a lower portion of the pillar bump 26A, while exposing an upper portion of the pillar bump 26A. In an embodiment, the molding compound 30 covers a lower portion of the metal pillar 26I, while exposing the upper portion of the metal pillar 26I and exposing the cap layer 26II.

The metal pillar 26I is a copper according to some embodiments. The copper pillar is intended to include substantially a material including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. The formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods. In an exemplary embodiment, the metal pillar 26I has a diameter less than about 50 μm. The thickness of the metal pillar 26I is less than about 50 μm, although the thickness may be greater or smaller.

The cap layer 26II is formed on the top of the metal pillar 26I. The metal cap layer 26II can include a solder layer, a metal layer, or combinations thereof. In an embodiment, the cap layer 26II is a solder layer made of Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, or SnAgSb, etc. Once a solder layer of tin has been formed on the structure, a reflow may be performed in order to shape the solder material into the desired shape. In an embodiment, the cap layer 26II includes a metal layer made of nickel, tin, tin-lead (SnPb), gold (Au), silver, palladium (Pd), indium (In), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu) or other similar materials or alloy. In an embodiment, the cap layer 26II includes a nickel layer and a solder layer. In an exemplary embodiment, the thickness of the cap layer 26II is about 1 μm to about 5 μm, although the thickness may be greater or smaller.

In manufacturing the pillar bump 26A, the metal pillar 26I can be formed as a round pillar, an oval pillar or an elongated pillar according to some embodiments. FIG. 6B is a top view of the metal pillar 26I formed of a round shape according to an embodiment. FIG. 6C is a top view of the metal pillar 26I formed of an elongated shape with two parallel sides and two curved ends according to an embodiment.

FIGS. 7˜12 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1-6.

With reference to FIG. 7, a first grooving process is performed on the wafer 100 to form a first groove 28 a on the scribe line region 12. The first grooving process removes portions of the second passivation layer 22, the first passivation layer 20, the dielectric layer 16 and the semiconductor substrate 14 within the scribe line regions 12. In an embodiment, the first groove 28 a of a width W1 penetrates the layers 22, 20 and 16 and reaches to a depth D1 of the semiconductor substrate 14. The depth D1 is less than the thickness T1 of the semiconductor substrate 14, and the width W1 is less than the width W2 of the scribe line region 12. In an embodiment, the depth D1 is equal to or greater than about 10 μm.

Next, as shown in FIG. 8, a second grooving process is performed on the wafer 100 to form a second groove 28 b inside the first groove 28 a on the scribe line region 12. The first grooving process removes portions of the semiconductor substrate 14 underlying the first groove 28 a. In an embodiment, the second groove 28 b of a width W3 penetrates the semiconductor substrate 14 and reaches to a depth D2 of the semiconductor substrate 14. In some embodiments, the depth D2 satisfies the formula: D1<D2<T1, and the width W3 satisfies the formula: W3<W1<W2.

Next, as shown in FIG. 9, a molding compound layer 30 is applied on the resulting structure depicted in FIG. 8 to cover the second passivation layer 22 and fill the grooves 28 a and 28 b, where each bump 26 is partially buried in the molding compound layer 30. In an embodiment, the molding compound layer 30 is in physical contact with a lower portion 26L of the bump 26, while the upper portion 26U of the bump 26 is exposed and protrudes from a top surface 30A of the molding compound layer 30. In some embodiments, the molding compound layer 30 may be in physical contact with the second passivation layer 22 and/or the UBM layers 24.

Then, as shown in FIG. 10, the wafer 100 is positioned upside down and attached to a tape 32, followed by performing a grinding process 34 on the backside of the semiconductor substrate 14, so as to thin down the thickness of the semiconductor substrate 14. The thinned substrate 14″ has a thickness T3 which is less than the thickness T1. In an embodiment, the thickness T3 is substantially equal to the depth D3 of the second groove 28 b, such that the molding compound layer 30 is exposed on the backside of the thinned substrate 14″. In some embodiments, the thickness T3 is greater than the depth D3 of the second groove 28 b. After detaching the tape 32, a singulation process is performed on the scribe line regions 12 to separate the individual chips 10 from the wafer 100. As depicted in FIG. 11, the dotted line 36 indicates the singulation process performed on the scribe line region 12, which passes through the molding compound layer 30 within the grooves 28 a and 28 b and passes through the semiconductor substrate 14 underlying the groove 28 b.

After the singulation process, the individual chip 10 is shown as FIG. 12. The molding compound layer 30 covers the lower portion 26L of the bump 26, the surface of the second passivation layer 22, and the sidewalls S22, S20 and S16 of the layers 22, 20 and 16. In addition, in the individual chip 10, the thinned substrate 14″ includes an upper sidewall 51 adjacent to the sidewall S16 of the dielectric layer 16, a lower sidewall S2 adjacent to the backside 14B of the thinned substrate 14″, and a surface region S3 extending from the upper sidewall S1 to the lower sidewall S2. The upper sidewall S1 and the surface region S3 are parts of the first groove 28 a created by the first grooving process, resulting in a recess region 14R at the edge of the thinned substrate 14″. The lower sidewall S2 is parts of the second groove 28 b created by the second grooving process. In an embodiment, the molding compound layer 30 covers the upper sidewall 51, the surface region S3 and the lower sidewall S2 of the thinned substrate 14″. In an embodiment, the molding compound layer 30 covers and fills the recess region 14R of the thinned substrate 14″.

For achieving fine pitch requirements, the bump 26 can be formed as a pillar bump according to some embodiments. FIG. 12A is a cross-sectional diagram illustrating the individual chip 10 with a pillar bump 26A. In an embodiment, the pillar bump 26A includes a metal pillar 26I formed on the UBM layer 24 and a cap layer 26II formed on the metal pillar 26I. The molding compound 30 covers a lower portion of the pillar bump 26A, while exposing an upper portion of the pillar bump 26A. In an embodiment, the molding compound 30 covers a lower portion of the metal pillar 26I, while exposing the upper portion of the metal pillar 26I and exposing the cap layer 26II.

The metal pillar 26I is a copper according to some embodiments. The copper pillar is intended to include substantially a material including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. The formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods. In an exemplary embodiment, the metal pillar 26I has a diameter less than about 50 μm. The thickness of the metal pillar 26I is less than about 50 μm, although the thickness may be greater or smaller. In manufacturing the pillar bump 26A, the metal pillar 26I can be formed as a round pillar, an oval pillar or an elongated pillar as illustrated in FIG. 6B and FIG. 6C according to some embodiments.

The cap layer 26II is formed on the top of the metal pillar 26I. The metal cap layer 26II can include a solder layer, a metal layer, or combinations thereof. In an embodiment, the cap layer 26II is a solder layer made of Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, or SnAgSb, etc. Once a solder layer of tin has been formed on the structure, a reflow may be performed in order to shape the solder material into the desired shape. In an embodiment, the cap layer 26II includes a metal layer made of nickel, tin, tin-lead (SnPb), gold (Au), silver, palladium (Pd), indium (In), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu) or other similar materials or alloy. In an embodiment, the cap layer 26II includes a nickel layer and a solder layer. In an exemplary embodiment, the thickness of the cap layer 26II is about 1 μm to about 5 μm, although the thickness may be greater or smaller.

FIGS. 13-15 are schematic diagrams illustrating a method of manufacturing a semiconductor package according to an embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1-6.

With reference to FIG. 13, a grooving process is performed on the wafer 100 to form a groove 28 c on the scribe line region 12. The grooving process removes portions of the second passivation layer 22, the first passivation layer 20 and the dielectric layer 16 within the scribe line regions 12, and the surface of the semiconductor substrate 14 is exposed. In an embodiment, the groove 28 c of a width W1 penetrates the layers 22, 20 and 16. The width W1 is less than the width W2 of the scribe line region 12.

Next, as shown in FIG. 14, a molding compound layer 30 is applied on the resulted structure to cover the second passivation layer 22 and fill the groove 28 c, where each bump 26 is partially buried in the molding compound layer 30. In an embodiment, the molding compound layer 30 is in physical contact with a lower portion 26L of the bump 26, while the upper portion 26U of the bump 26 is exposed and protrudes from a top surface 30A of the molding compound layer 30. In some embodiments, the molding compound layer 30 may be in physical contact with the second passivation layer 22 and/or the UBM layers 24.

After thinning process and singulation process, the individual chip 10 is shown as FIG. 15. The molding compound layer 30 covers the lower portion 26L of the bump 26, the surface of the second passivation layer 22, and the sidewalls S22, S20 and S16 of the layers 22, 20 and 16. In addition, in the individual chip 10, the sidewall S2 of the thinned substrate 14″ is substantially leveled with the sidewall S30 of the molding compound layer 30.

For achieving fine pitch requirements, the bump 26 can be formed as a pillar bump according to some embodiments. FIG. 15A is a cross-sectional diagram illustrating the individual chip 10 with a pillar bump 26A. In an embodiment, the pillar bump 26A includes a metal pillar 26I formed on the UBM layer 24 and a cap layer 26II formed on the metal pillar 26I. The molding compound 30 covers a lower portion of the pillar bump 26A, while exposing an upper portion of the pillar bump 26A. In an embodiment, the molding compound 30 covers a lower portion of the metal pillar 26I, while exposing the upper portion of the metal pillar 26I and exposing the cap layer 26II.

The metal pillar 26I is a copper according to some embodiments. The copper pillar is intended to include substantially a material including pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. The formation methods may include sputtering, printing, electro plating, electroless plating, and commonly used chemical vapor deposition (CVD) methods. In an exemplary embodiment, the metal pillar 26I has a diameter less than about 50 μm. The thickness of the metal pillar 26I is less than about 50 μm, although the thickness may be greater or smaller. In manufacturing the pillar bump 26A, the metal pillar 26I can be formed as a round pillar, an oval pillar or an elongated pillar as illustrated in FIG. 6B and FIG. 6C according to some embodiments.

The cap layer 26II is formed on the top of the metal pillar 26I. The metal cap layer 26II can include a solder layer, a metal layer, or combinations thereof. In an embodiment, the cap layer 26II is a solder layer made of Sn, SnAg, —Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, or SnAgSb, etc. Once a solder layer of tin has been formed on the structure, a reflow may be performed in order to shape the solder material into the desired shape. In an embodiment, the cap layer 26II includes a metal layer made of nickel, tin, tin-lead (SnPb), gold (Au), silver, palladium (Pd), indium (In), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu) or other similar materials or alloy. In an embodiment, the cap layer 26II includes a nickel layer and a solder layer. In an exemplary embodiment, the thickness of the cap layer 26II is about 1 μm to about 5 μm, although the thickness may be greater or smaller.

According to the embodiments, a semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. The bump includes a metal pillar and a cap layer. A sidewall of the passivation layer is covered by the molding compound layer.

According to some embodiments, a method of forming a semiconductor package includes forming a passivation layer overlying a semiconductor substrate which includes a first chip region, a second chip region and a scribe line region positioned between the first chip region and the second chip region. A bump is then formed overlying the passivation layer on at least one of the first chip region and the second chip region. The bump includes a metal pillar and a cap layer. Next, a groove is formed to pass through the passivation layer on the scribe line region. Then a molding compound layer is formed to cover the passivation layer and a lower portion of the bump and fill the groove. After performing a singulation process on the scribe line region, the first chip region is separated from the second chip region.

According to some embodiments, a semiconductor package includes a dielectric layer overlying a substrate, a contact pad overlying the dielectric layer, a passivation layer overlying the contact pad, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. The bump includes a metal pillar and a cap layer. The sidewalls of the passivation layer and the dielectric layer are covered by the molding compound layer.

While the present disclosure has been particularly shown and described with reference to example embodiments thereof, a skilled person in the art will appreciate that there can be many embodiment variations of this disclosure. Although the embodiments and their features have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments.

The above method embodiments show exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure. 

What is claimed is:
 1. A semiconductor package, comprising: a chip comprising: a semiconductor substrate; a passivation layer overlying the semiconductor substrate; and a bump overlying the passivation layer, wherein the bump comprises a metal pillar and a cap layer on the metal pillar; and a molding compound layer overlying the passivation layer and covering a lower portion of the bump; wherein a sidewall of the passivation layer is covered by the molding compound layer.
 2. The semiconductor package of claim 1, wherein the semiconductor substrate comprises an upper sidewall adjacent to the sidewall of the passivation layer, a lower sidewall adjacent to the backside of the semiconductor substrate, and a surface region extending from the upper sidewall to the lower sidewall, and the upper sidewall and the surface region form a recessed region in the semiconductor substrate.
 3. The semiconductor package of claim 2, wherein the molding compound layer covers the upper sidewall and the surface region of the semiconductor substrate.
 4. The semiconductor package of claim 2, wherein the recessed region is filled with the molding compound layer.
 5. The semiconductor package of claim 2, wherein the lower sidewall of the semiconductor substrate is substantially leveled with a sidewall of the molding compound layer.
 6. The semiconductor package of claim 2, wherein the upper sidewall of the semiconductor substrate is substantially leveled with the sidewall of the passivation layer.
 7. The semiconductor package of claim 2, wherein the molding compound layer covers the lower sidewall of the semiconductor substrate
 8. The semiconductor package of claim 1, wherein an upper portion of the bump protrudes from a top surface of the molding compound layer.
 9. A method of forming a semiconductor package, comprising: forming a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate comprises a first chip region, a second chip region and a scribe line region positioned between the first chip region and the second chip region; forming a bump overlying the passivation layer on at least one of the first chip region and the second chip region, wherein the bump comprises a copper pillar and a cap layer; forming a groove passing through the passivation layer on the scribe line region; forming a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove; and performing a singulation process on the scribe line region to separate the first chip region from the second chip region.
 10. The method of claim 9, wherein the groove extends to a portion of the semiconductor substrate on the scribe line region.
 11. The method of claim 10, wherein the formation of the groove comprising: performing a first grooving process to form the groove passing through the passivation layer and extending to a first depth of the semiconductor substrate on the scribe line region, wherein the method further comprises: performing a second grooving process to form another groove underlying the groove extending to a second depth of the semiconductor substrate on the scribe line region.
 12. The method of claim 11, wherein the groove has a first width, the another groove has a second width, and the first width is greater than the second width.
 13. The method of claim 9, wherein the formation of the molding compound layer comprises applying a liquid molding compound on the semiconductor substrate.
 14. The method of claim 9, further comprising thinning the semiconductor substrate before performing the singulation process.
 15. A semiconductor package, comprising: a chip comprising: a substrate; a dielectric layer overlying the substrate; a contact pad overlying the dielectric layer; a passivation layer overlying the contact pad; and a bump overlying the passivation layer, wherein the bump comprises a copper pillar and a cap layer on the copper pillar; and a molding compound layer overlying the passivation layer and covering a lower portion of the bump; wherein sidewalls of the passivation layer and the dielectric layer are covered by the molding compound layer.
 16. The semiconductor package of claim 15, wherein the substrate comprises an upper sidewall adjacent to the sidewall of the dielectric layer, a lower sidewall adjacent to the backside of the semiconductor substrate, and a surface region extending from the upper sidewall to the lower sidewall, and the upper sidewall and the surface region are covered by the molding compound layer.
 17. The semiconductor package of claim 16, wherein the upper sidewall and the surface region form a recessed region in the semiconductor substrate, and the molding compound layer fills the recessed region.
 18. The semiconductor package of claim 16, wherein the upper sidewall of the semiconductor substrate is substantially leveled with the sidewall of the dielectric layer.
 19. The semiconductor package of claim 16, wherein the molding compound layer covers the lower sidewall of the semiconductor substrate.
 20. The semiconductor package of claim 15, wherein a sidewall of the semiconductor substrate is substantially leveled with a sidewall of the molding compound layer. 